The present invention generally relates to semiconductor devices and more particularly to a flash-erasable EPROM device or simply a flash memory device that has an improved reliability.
In relation to the storage device of computers, there is a continuous demand for a non-volatile semiconductor memory device having a large capacity for storing information. Particularly, the so-called flash-erasable memory device or simply flash memory device has been studied intensively in recent years as an alternative of hard disk devices. In flash memory devices, rewriting of data is possible similarly to the conventional random access memories, while the device can hold the written information even when the electrical power is turned off. Thus, the device is ideal for external storage device of computers such as a hard disk. Further, application to the memory cards is studied. In relation to various applications of the flash memory device, intensive efforts are in progress to improve the reliability of the device.
FIG. 1 shows the structure of a typical memory cell transistor that forms a flash memory device.
Referring to FIG. 1, the memory cell transistor is constructed on a semiconductor substrate 1 and includes a source region 6 and a drain region 7 formed in the substrate 1 similarly to a conventional MOS transistor. On the upper major surface of the substrate 1, a gate insulation film 2 is provided to cover the channel region extending between the source region 6 and the drain region 7, and a gate electrode 3 is formed on the gate insulation film 2 in correspondence to the channel region of the device. Further, a capacitor insulation film 4 is provided to surround the gate electrode 3, and the gate electrode 3 thereby forms a floating gate electrode. Further, an electrode 5 is provided on the floating gate electrode 3 such that the electrode 5 is insulated from the electrode 3 by the capacitor insulation film 4. Thereby, the electrode 5 is used as a control electrode.
Hereinafter, the operation of a flash memory of the NOR type will be described.
When writing data, a predetermined drive voltage is applied across the source region 6 and the drain region 7 such that the electrons are caused to flow from the source region 6 to the drain region 7. Simultaneously, a large positive voltage is applied to the control electrode 5 to induce a large electric field between the floating gate electrode 3 and the substrate 1. Thereby, the electrons transported along the channel region and accelerated in the vicinity of the drain region 7 are injected into the floating gate electrode 3 through the gate insulation film 2 as hot electrons. Once the electrons are injected, the electric charges associated with the electrons controls the conduction of the channel region between the source and drain regions 6 and 7. In other words, one can read the content of the data written into the memory cell transistor by detecting the conduction thereof. When erasing data, on the other hand, a large electric field is induced between the floating gate 3 and the source region 6 by applying a large positive voltage to the source region 6. Thereby, the electrons in the floating gate 3 dissipate into the source region 6 by causing a tunneling through the gate insulation film 2.
FIG. 2 shows the foregoing control scheme of the flash memory device for the writing mode for wiring data into the memory cell, the reading mode for reading data from the memory cell, and the erasing mode for erasing data from the memory cell, wherein the voltage VH is set typically to +12 volts, while the voltage V.sub.M may be set to +6 volts. Further, the voltage V.sub.L is set to about +5 volts.
FIG. 3 shows the overall construction of a typical flash memory device.
Referring to FIG. 3, the device includes a memory cell array 11 in which a plurality of memory cell transistors each having a construction of FIG. 1 are arranged in rows and columns, and the memory cell in the memory cell array 11 is selected in response to address data that is supplied to a row address buffer circuit 12 for activating a row decoder 13 and a column address buffer circuit 14 for activating a column decoder 15. There, the row decoder 13 selects a word line WL in response to the row address data latched in the row address buffer circuit 12 while the column decoder 15 controls a column selection gate 16 to select a bit line BL in response to the column address data that is latched in the column address buffer circuit 14.
In order to achieve inputting and outputting of data, there is provided a data bus 17 connected to an input/output buffer circuit 18, and the data on the bus 17 is written into a selected memory cell such as the memory cell 11a via a write amplifier 19 and the column selection gate 16. On the other hand, the data stored in the selected memory cell is transferred to the input/output buffer circuit 18 via the column selection gate 16 and a sense amplifier 20. Further, in order to control the read/write operation of the memory device, there is provided another buffer circuit 21 that is supplied with an output enable signal /OE, a chip enable signal /CE, and further with a write enable signal /WE, wherein the signal /OE is used for enabling the data output of the input/output buffer circuit 18, the signal /CE is used for the chip selection, and the signal /WE is used for enabling the writing of data into the selected memory cell.
Further, there is provided an erase power supply unit 22 that characterizes the NOR type flash memory device, wherein the power supply unit 22 supplies a predetermined erase voltage when erasing the data from the memory cell array. As is well known, the erasing of data occurs simultaneously for all the memory cells in the memory cell array 11 in the flash memory device. In addition, in order to control the operation of memory cell device including the erase power supply 22, a controller 23 is provided. There, the controller 23 is supplied with data from the data bus 17 as well as an output of the buffer circuit 21 and controls the read/write as well as erase operation of the device.
FIG. 4 shows the writing of data into the memory cell transistor of FIG. 1, wherein the vertical axis represents the drain current and the horizontal axis represents the drain voltage. As already noted with reference to FIG. 2, the voltage V.sub.D is applied to the drain region during the writing process of data, while the voltage V.sub.H is applied simultaneously to the control gate.
Referring to FIG. 4, it will be noted that the drain current increases in an interval designated as "1" with increasing drain voltage V.sub.D, while the drain current decreases suddenly in correspondence to the interval designated as "2" with further increase in the drain voltage V.sub.D. In correspondence to this negative bump of the drain current, the injection of electrons into the floating gate electrode occurs. Further, when the drain voltage V.sub.D has reached an avalanche voltage V.sub.ABD, an avalanche breakdown occurs in the channel region of the memory cell transistor and the drain current increases steeply. Thereby, an efficient injection of the electrons is achieved into the floating gate. Thus, the flash memory device generally uses the avalanche voltage V.sub.ABD for the voltage V.sub.M shown in FIG. 2 to achieve an efficient writing of the data. In fact, the drain voltage V.sub.D is clamped at the level V.sub.ABD when the foregoing positive control voltage V.sub.H is applied to the control gate.
On the other hand, when the voltage of the control gate is low or zero in correspondence to an operational state of the device wherein no writing of data occurs, the drain current changes as shown in the broken line in FIG. 4. There, the drain current remains low until a breakdown voltage V.sub.JCT is reached. In response to the voltage V.sub.JCT, a breakdown occurs at the p-n junction between the drain region and the substrate. Generally, the voltage V.sub.JCT is larger than V.sub.ABD by more than one volt. Thereby, there can occur a possibility that the writing of data into a first memory cell transistor can affect the operation of a second memory transistor that shares the power supply line commonly with the memory cell transistor. It should be noted that the large drain voltage applied to the first memory cell transistor for writing data induces a large electric field between the drain region and the floating gate in the second memory cell transistor. Thereby, the electric charges stored in the second memory cell transistor can dissipate into the drain of the same memory cell transistor and the data held therein is destroyed. This interference of memory cell transistors is known as disturbance."
Further, the conventional flash memory device has suffered from the problem of limited flexibility in the design of redundant construction in that only the column redundancy is possible as shown in FIG. 5.
Referring to FIG. 5, the drawing corresponds to FIG. 3 and includes the memory cell array 11 that in turn includes a number of memory cells M.sub.1,1 -M.sub.2,3 provided in correspondence to intersections of word lines WL.sub.1 -WL.sub.2 and bit lines BL.sub.1 -BL.sub.3. In FIG. 5, those parts corresponding to the parts described previously are designated by the same reference numerals and the description will be omitted. It will be noted that the column selection gate 16 includes transfer gate transistors Tsw.sub.1 -Tsw.sub.3 for selecting the bit lines BL.sub.1 -BL.sub.3 respectively.
In the memory cell array 11 of FIG. 5, it will be noted that there is provided another transfer gate transistor Tsw.sub.4 that is activated in response to an output of a decoder 24 for selecting another bit line BL.sub.4, and a column redundant memory cell array 11.sub.CR is provided in connection to the bit line BL.sub.4. There, the redundant memory cell array 11.sub.CR includes memory cell transistors M.sub.1,4 and M.sub.2,4 having respective drains connected commonly to the bit line BL.sub.4 and the memory cell array 11.sub.CR is activated in response to the output of the redundant decoder 24 that in turn is controlled by a defect detection circuit 25. There, the circuit is supplied with the column address data from a column buffer circuit 14 and compares the same with the address data for defective memory cells stored in a memory device not illustrated. When the address data indicates the selection of a defective memory cell, the circuit 25 activates the redundant decoder 24 that in turn selects the redundant bit line BL.sub.4. It should be noted that such a redundant memory cell array may be provided as a part of a utility memory cell array that is provided separately from the real memory cell array for various purposes such as testing. In other words, one can use such a memory cell array 11 .sub.c R also for testing as will be discussed later with reference to the embodiment of the present invention.
In such a conventional flash memory device, it is desirable to provide a row redundant memory cell array in addition to the column redundant memory cell array 11.sub.CR for increasing the degree of freedom for saving the defect in the memory cells. However, such a construction of row redundant memory cell array has been generally impossible in the flash memory devices. Hereinafter, the reason of this undesirable situation will be examined briefly.
In the flash memory devices, the electric charges are removed from the floating gate each time the data stored in the memory cell is erased. As already noted, such an erasing process is conducted by applying a positive voltage to the source region. Thereby, all the memory cells that are connected commonly to the source supply voltage experience dissipation of the electric charges from the floating gate. In other words, the data stored in the memory cells that form the memory cell array of the device are erased simultaneously.
Another point that requires special attention in the flash memory devices is that the dissipation of electrons from the floating gate should be achieved in such a manner that no substantial electric charges remain in the floating gate after the erasing of data has occurred in the memory cell. When the removal of electrons is excessive, the floating gate may charge positively and the memory cell transistor is turned on permanently. In order to avoid this problem of "excessive erasing," it is generally practiced to write data "0" into the memory cell by injecting electrons to the floating gate before each erasing process of data.
Thus, when a row redundant memory cell array is constructed by modifying the circuit of FIG. 5, for example such that the word line WL.sub.2 is selected in place of the word line WL.sub.1 for saving defective memory cells connected to the word line WL.sub.1, the writing of the data "0" does not occur to the memory cells connected to the word line WL.sub.1. On the other hand, the removal of the electric charges occurs also in these memory cells in response to the erasing process, as these memory cells are connected also to the erase power supply unit 22. Thereby, the memory cell transistors M.sub.1,1 -M.sub.1,4 connected to the word line WL.sub.1 are inevitably erased excessively as a result of the excessive removal of the electrons to the drain region. When this occurs, the floating gate is injected with holes and the memory cell transistors take a permanently turned-on state. As the transistors M.sub.1,1 -M.sub.1,4 are connected to the bit lines BL.sub.1 -BL.sub.4, such an erroneous turning-on of the memory cell transistors inevitably causes a erroneous voltage level of the bit lines and the overall operation of the flash memory device becomes defective.
In the conventional flash memory devices having the column redundancy as shown in FIG. 5, it is proposed to divide the memory cell array into a plurality of blocks each driven by an independent power supply unit such that the simultaneous erasing of data occurs only in each block instead of the entirety of the memory cell array. When the column redundancy is applied to such a device, however, the redundant memory cell columns are provided in each block and there arises an inconvenience in that a substantial device area is occupied by the redundant memory cell columns. Thereby, there is a demand to reduce the area of the device that is occupied by the redundant memory cell column.
In the conventional memory devices such as dynamic random access memories or static random access memories, it has been practiced to provide a utility memory cell block for testing the device. Such a utility block is used for example for the purpose of guaranteeing a predetermined number of times for the rewriting of data into the memory cell transistors forming the memory cell array. In the flash memory devices, however, erasing of data is achieved in the ordinary, "real" memory cell block each time the data is erased from the utility memory cell block, as long as the memory cell transistors in the real memory cell block share the electric power supply with the memory cell transistors in the utility memory cell block. Thereby, the memory cell transistors in the real memory cell block are erased excessively and the proper read/write operation of the device is no longer possible. In other words, the conventional flash memory devices have suffered from the problem that the test for guaranteeing the number of times the write operation can be achieved properly is impossible.
In addition, in the conventional flash memory devices, there has been a problem in that one has to design the device to have a relatively large channel length in correspondence to the relatively large voltage applied to the source region for erasing data from the memory cell transistors, such that a sufficient junction breakdown voltage is secured. On the other hand, such a large channel length inevitably imposes a problem in the miniaturization of the device. Thus, it is desired to reduce the magnitude of the voltage that is applied to the memory cell transistor for erasing information therefrom.